1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor integrated circuit (IC) having a stacked capacitor cell, and more specifically to a method of fabricating an IC circuit having a capacitor whose surface is rendered porous for increasing an effective charge storage area.
2. Description of the Related Art
As is known in the art, a storage capacitor is provided in each dynamic random access memory (DRAM) cell. In order to meet an ever-increasing demand for higher packaging density, it is a current practice to configure each storage capacitor in a three-dimensional structure. Generally, there are two types of three-dimensional capacitor cells, one of which is a stacked capacitor cell and the other is a trenched capacitor cell.
With increase in miniaturization of semiconductor devices such as 64 M-bit or higher bit density DRAM, a capacitor storage area becomes strictly limited. Accordingly, in order to adequately meet such a tendency, it has been proposed to use, as a capacitor dielectric film, tantalum oxide (Ta.sub.2 O.sub.5) of high permittivity in place of silicon oxide or silicon nitride. In this case, in order to prevent undesirable reaction between the Ta.sub.2 O.sub.5 film and polysilicon film (forming a lower capacitor electrode) and also to prevent forming of a silicon oxide film therebetween, it has been proposed to provide titanium nitride between the Ta.sub.2 O.sub.5 film and the polysilicon film.
Before turning to the present invention, a brief description of a first conventional technique of fabricating a stacked capacitor cell is given with reference to FIGS. 1A-1G. This first conventional technique is disclosed in Japanese Laid-open Patent Application No. 4-101453.
The sequence of fabricating the stacked capacitor cell, shown in FIGS. 1A-1G, starts with preparation of a silicon substrate 10. A silicon oxide film 12 is then deposited on the top surface of the substrate 10 for electrically isolating a capacitor from other circuit components. A contact hole 14 is formed in the silicon oxide film 12 using known lithographic and dry etching techniques. A polysilicon film 16 is then deposited in a manner to electrically contact a part of the top surface of the silicon substrate 10 through the hole 14 as illustrated in FIG. 1A. Thereafter, an impurity such as phosphorous is doped into the polysilicon film 16 which serves as a lower electrode of the capacitor.
The structure shown in FIG. 1A is then subjected to preprocessing and/or cleaning for removing native oxides on the polysilicon film 16. Thereafter, a titanium film 18 is deposited, using sputtering (for example), on the entire top surface of the structure as shown in FIG. 1B. In the above, in the pre-processing, dilute hydrofluoric acid, or a mixed solution of hydrofluoric acid and ammonium fluoride, is used. On the other hand, in the cleaning, a so-called RCA cleaning (viz., cleaning techniques proposed by Radio Corporation of America) is used wherein a mixed solution of hydrogen peroxide and ammonia or a mixed solution of hydrogen peroxide and sulfuric acid is used.
Subsequently, the structure shown in FIG. 1A is annealed at temperatures between 500.degree. C. and 700.degree. C. and in an atmosphere of nitrogen or ammonia, or in an atmosphere of mixed gases of nitrogen and ammonia. Thus, as shown in FIG. 1C, the titanium film 18 on the lower electrode 16 changes to a titanium silicide (TiSi.sub.2) film 20, while the titanium film 18 on the silicon oxide film 12 changes to a titanium nitride film 22. The resultant structure thus obtained is immersed in a water solution containing ammonia and hydrogen peroxide, whereby the titanium nitride film 22 is selectively removed as shown in FIG. 1D.
The structure shown in FIG. 1D is then subjected to annealing at temperatures between 800.degree. C. and 1000.degree. C. in a gas atmosphere of nitrogen or ammonia or in a mixed gas atmosphere of nitrogen and ammonia. Thus, the titanium silicide film 20 changes to a titanium nitride film 24. Following this, as shown in FIG. 1F, a Ta.sub.2 O.sub.5 film 28 of about 5 to 50 nm thick is deposited onto the top surface of the structure of FIG. 1E using a spattering or chemical vapor deposition (CVD) technique. The Ta.sub.2 O.sub.5 film 28 serves as a capacitor dielectric film. As shown in FIG. 1G, an upper capacitor electrode 28 is then formed on the Ta.sub.2 O.sub.5 film 26 in the same manner as the lower electrode was formed, whereby the capacitor is formed on the substrate 10.
As mentioned above, the Ta.sub.2 O.sub.5 film 26 is used as a capacitor dielectric film. It is therefore necessary to provide the titanium nitride film 24 between the polysilicon film (viz., lower capacitor electrode) 16 and the Ta.sub.2 O.sub.5 film 26 in order to prevent undesirable reaction between the films 16 and 26 or to prevent a silicon oxide from being grown in the boundary therebetween. As a result, the conventional method has suffered from the problem that the processing step of forming the titanium nitride film 24 is required.
In addition to the first conventional method, in order to meet recent requirements of increasing an effective capacitance area of the lower electrode in a giga-bit memory cell, a technique of depositing a plurality of hemisphere grids (HSGs) on the lower electrode has been proposed. By way of example, such a technique is disclosed in a paper entitled "1 GDRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET" by K. Shibahara, et al., International Electron Devices Meeting 1994, pages 639-642. According to this second conventional technique, after a plurality of HSGs are grown on the surface of a lower capacitance electrode, a Ta.sub.2 O.sub.5 dielectric film is deposited on the lower electrode. However, in order to eliminate the same problems as mentioned in connection with the first prior art, a titanium nitride layer is provided between the polysilicon film (viz., lower electrode) and the Ta.sub.2 O.sub.5 dielectric film.
Prior to forming the titanium nitride film, the lower electrode should be subjected to pretreatment and cleaning processes in order to remove native (nature) oxide(s). These processes tend to etch top portion of each HSG with the result of reducing the effective storage area of the lower electrode. In other words, the porous surface of the electrode is gradually rendered smoothed with each cleaning process. Further, the degree of lowering the storage area depends on the number of pretreatment and cleaning processes, which leads to scattering of resulting capacitance values with different lots.